Complementary metal oxide semiconductor (CMOS) transistors are the building blocks for integrated circuits (ICs). CMOS devices continue to be scaled to smaller sizes with the goals of increasing both device speed and IC density. Exemplary CMOS devices include N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS) transistors. A CMOS transistor generally comprises a semiconductor substrate, a channel layer above the semiconductor substrate, a gate oxide layer and a gate stack above the channel layer, and source and drain diffusion regions in the surface of the semiconductor substrate. Contacts are made to the gate stack and to both the source and drain regions of the transistor.
It is often necessary to align structures fabricated at different lithographic stages of IC fabrication. Such structures can be self-aligned, that is, one structure is forced into a specific position relative to another structure for a wide range of lithographically defined positions. For example, the self-aligned implant of a source and drain to a polysilicon gate has been used to achieve submicron precision in the placement of exemplary CMOS devices. In ICs, contact to the source and/or drain of CMOS devices is necessary to incorporate them into functioning circuits. Contact is normally made through an overlying layer of dielectric material. If, however, the contact holes are misaligned with respect to the gate, a short can result.
Conventional lithographic processes, e.g., contact etching processes, include contact etch stop layers and middle etch stop layers. Such conventional processes, however, can result in contact misalignment caused by topography variations in the IC.